This invention relates generally to pulldown circuits for sense amplifiers in a dynamic random access memory ("DRAM"), and, more particularly, to a pulldown circuit that minimizes ground noise at high power supply voltages while maintaining normal operation at lower, normal power supply voltages.
A portion 10 of a basic DRAM configuration is shown in FIG. 1. One memory cell 12 from an array is coupled to a sense amplifier 14, which is controlled by a pulldown circuit 16. The memory cell includes an N-channel transistor 24 and storage capacitor 26. The gate of transistor 24 is coupled to a "word" line 22 and the drain of transistor 24 is coupled to a "digit" line 18. The word and digit lines are used to uniquely address other memory cells in the DRAM memory array. A complementary digit line 20 is either coupled to a reference voltage or senses complementary data to that stored in memory cell 12. The sense amplifier 14 includes a pair of N-channel sense amplifier transistors Q1 and Q2 having a cross-coupled gate and drain configuration that form the complementary digit lines 18 and 20. As is known in the art, transistors Q1 and Q2 sense the slight charge differential between the digit lines provided by the memory cells in the DRAM array. The positive feedback of the cross-coupled configuration amplifies the charge differential into full valid logic levels at digit lines 18 and 20. Several sense amplifiers 14 can be coupled to common node 25, each sense amplifier corresponding to a column of memory cells 12 in the DRAM memory array. The pulldown circuit 16 is typically an N-channel transistor in which the drain is coupled to node 25 and the source is coupled to ground. An input signal derived from an internal sense amplifier enable signal drives the gate of the transistor, which ultimately drives node 25 to ground, enabling the operation of sense amplifier 14.
A more sophisticated prior art sense amplifier pulldown circuit is taught in U.S. Pat. No. 5,042,011 ("'011") to Casper et al, entitled "Sense Amplifier Pulldown Device with Tailored Edge Input", which is hereby incorporated by reference. The pulldown circuit taught in the '011 U.S. Pat. No. minimizes noise on the digits lines 18 and 20 due to capacitive coupling through the sense amplifier 14 by tailoring the pulldown waveform characteristic.
A schematic diagram of the pulldown circuit is shown in FIG. 2A. In addition to a single N-channel pulldown transistor Q5, the pulldown circuit of FIG. 2A includes an inverter stage for controlling the rise time of the gate input signal "B", which in turn tailors the pulldown waveform "C" at node 25. The inverter stage includes a P-channel pullup transistor Q3 and an N-channel pulldown transistor Q4, wherein the ratio of the size of the pullup transistor Q3 to the size of the pulldown transistor is approximately 0.8. The gates of the transistors Q3 and Q4 are coupled together at node 30 to receive an inverter input signal "A", which is derived from the internal DRAM sense amp enable signal. The drains of transistors Q3 and Q4 are coupled together to form the inverting output. The source of transistor Q3 is coupled to a source of power supply voltage, VDD, at node 28. The power supply voltage has a typical nominal value of five volts. The source of transistor Q4 is coupled to ground.
In operation, the week pullup ability of transistor Q3 controls the rise time of the gate input signal B, which in turn controls the time at which pulldown transistor Q5 fully conducts. Referring now to FIG. 2B, the inverter input waveform A is shown as a negative-going step signal that initiates the action of the pulldown circuit at time T1. Subsequent to time T1, the gate input signal B begins to slowly rise with a rise time determined by the size of transistor Q3. Correspondingly, the pulldown waveform C begins to slowly fall from a previously equilibrated level of VDD/2. The initial movement of the pulldown waveform C is sufficient to enable the sense amp to begin charge sensing, but without an undesirable coupling of the pulldown waveform on to the digit lines 18 and 20. At time T2, once the digit lines begin to move slightly, the positive feedback renders the sense amplifier 14 fully operational and establishes full logic levels and digit lines 18 and 20. The full current provided by the sense amplifier 14 flows through pulldown transistor Q5, and thus common node 25 is quickly discharged to ground at time T3.
While the pulldown circuit shown in FIG. 2A represents an improvement beyond a sole pulldown transistor Q5, a problem remains when the power supply voltage VDD coupled to the DRAM is set to voltages above five volts. Typically, the VDD power supply can be set as high as six volts without causing damage to the DRAM. However, at these high power supply voltages, the internal ground lines in the DRAM can move as much as 0.5 volts during a CAS operation (column address strobe), when all the sense amplifiers 14 are activated. The amount of movement of the internal ground lines away from earth ground is related to the amount that the VDD power supply is above the nominal five volt level. The internal ground lines can have significant resistance, thus developing an associated voltage when the charge on the digit lines is quickly discharged through the sense amplifiers 14. The instantaneous current flowing into the parasitic internal ground resistance, which develops the ground voltage, is proportional to the VDD power supply voltage.
It is undesirable for the internal ground lines associated with the sense amplifiers to move away from zero volts because other DRAM circuitry may be referenced to that ground line. For example, if an input address buffer is referenced to an internal ground lines that moves to 0.5 volts during the CAS operation, data errors can result. Since the external source of read or write addresses is referenced to earth ground, a mismatch in logic levels can occur. The desired address for reading or writing data could be corrupted by the DRAM, resulting in data being written into or read from, an incorrect memory address. Other similar data errors are possible depending upon the particular DRAM architecture.
Accordingly, a need remains for a pulldown circuit for a sense amplifier in a DRAM that conditions the pulldown waveform in response to the VDD supply voltage in order to minimize internal ground line bounce or noise.